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14 results

    • Seminar

    • Cryptography

    Module Learning With Errors and Structured Extrapolated Dihedral Cosets

    • October 02, 2026 (13:45 - 14:45)

    • Batiment 32A salle 8

    Speaker : Jinwei Zheng - Télécom Paris

    The Module Learning With Errors (MLWE) problem is the fundamental hardness assumption underlying the key encapsulation and signature schemes ML-KEM and ML-DSA, which have been selected by NIST for post-quantum cryptography standardization. Understanding its quantum hardness is crucial for assessing the security of these standardized schemes.   Inspired by the equivalence between LWE and[…]

    • Cryptography

    • Seminar

    • Databases

    • Machine learning

    • Economics

    • Law

    • Strategy

    • Information flow control

    TBA

    • October 16, 2026 (09:00 - 10:00)

    • Inria Center of the University of Rennes

    • Seminar

    • SemSecuElec

    Securing processor's microarchitecture against SCA in a post-quantum cryptography setting

    • October 16, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Vincent MIGLIORE - LAAS-CNRS

    Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]

    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

    • Seminar

    • Databases

    • Machine learning

    • Economics

    • Law

    • Strategy

    • Information flow control

    TBA

    • November 13, 2026 (09:00 - 10:00)

    • Inria Center of the University of Rennes

    Speaker : Chine LABBE - NewsGuard

    • Seminar

    • SemSecuElec

    Onysis: A secure European SoC FPGA 

    • November 13, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Adrien GRASSEIN - Nanoxplore

    Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]

    • SemSecuElec

    • Seminar

    • SemSecuElec

    Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components

    • November 13, 2026 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Luc NOIZETTE - Nuclétudes (filiale Ariane group)

    This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform.  A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks.  Applying it to test softwares[…]

    • SemSecuElec

    • Fault injection

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