Advances in cryptographic coprocessor design on FPGAs

Security in embedded systems requires the choice of a suitable implementation platform. For some systems, a general purpose microprocessor satisfies the requirements, but when high performance is the main criterium, cryptographic coprocessors in hardware are indispensable. When very high performance is required or when a high volume of coprocessors is needed, ASICs (Application Specific Integrated Circuits) are chosen as implementation platforms. In this case, the reconfigurability of FPGAs (Field Programmable Gate Arrays) is only used for prototyping. However, because of the efforts of FPGA manufacturing companies, the performance gap between ASICs and FPGAs becomes smaller and smaller. FPGAs have become heterogeneous systems with a variety of dedicated resources such as multiplier blocks, DSP slices, RAM blocks,... This explains the trend that FPGAs are more and more used as end products. Following this trend, the need for specific FPGA architectures can be justified. This presentation focuses on cryptographic coprocessor design, optimized for FPGAs.