Description
Security in embedded systems requires the choice of a suitable implementation platform. For some systems, a general purpose microprocessor satisfies the requirements, but when high performance is the main criterium, cryptographic coprocessors in hardware are indispensable. When very high performance is required or when a high volume of coprocessors is needed, ASICs (Application Specific Integrated Circuits) are chosen as implementation platforms. In this case, the reconfigurability of FPGAs (Field Programmable Gate Arrays) is only used for prototyping. However, because of the efforts of FPGA manufacturing companies, the performance gap between ASICs and FPGAs becomes smaller and smaller. FPGAs have become heterogeneous systems with a variety of dedicated resources such as multiplier blocks, DSP slices, RAM blocks,... This explains the trend that FPGAs are more and more used as end products. Following this trend, the need for specific FPGA architectures can be justified. This presentation focuses on cryptographic coprocessor design, optimized for FPGAs.
Next sessions
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Efficient zero-knowledge proofs and arguments in the CL framework
Speaker : Agathe Beaugrand - Institut de Mathématiques de Bordeaux
The CL encryption scheme, proposed in 2015 by Castagnos and Laguillaumie, is a linearly homomorphic encryption scheme, based on class groups of imaginary quadratic fields. The specificity of these groups is that their order is hard to compute, which means it can be considered unknown. This particularity, while being key in the security of the scheme, brings technical challenges in working with CL,[…] -
Constant-time lattice reduction for SQIsign
Speaker : Sina Schaeffler - IBM Research
SQIsign is an isogeny-based signature scheme which has recently advanced to round 2 of NIST's call for additional post-quantum signatures. A central operation in SQIsign is lattice reduction of special full-rank lattices in dimension 4. As these input lattices are secret, this computation must be protected against side-channel attacks. However, known lattice reduction algorithms like the famous[…] -
Circuit optimisation problems in the context of homomorphic encryption
Speaker : Sergiu Carpov - Arcium
Fully homomorphic encryption (FHE) is an encryption scheme that enables the direct execution of arbitrary computations on encrypted data. The first generation of FHE schemes began with Gentry's groundbreaking work in 2019. It relies on a technique called bootstrapping, which reduces noise in FHE ciphertexts. This construction theoretically enables the execution of any arithmetic circuit, but[…] -
Cycles of pairing-friendly abelian varieties
Speaker : Maria Corte-Real Santos - ENS Lyon
A promising avenue for realising scalable proof systems relies on the existence of 2-cycles of pairing-friendly elliptic curves. More specifically, such a cycle consists of two elliptic curves E/Fp and E’/Fq that both have a low embedding degree and also satisfy q = #E(Fp) and p = #E’(Fq). These constraints turn out to be rather restrictive; in the decade that has passed since 2-cycles were first[…]-
Cryptography
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