Table of contents

Description

Embedded electronic systems and their associated softwares are used in an always increasing number of daily life, industrial and government applications. The security of these systems is a major societal, economic and sovereignty issue. This leads to increasingly activities in research and development by scientists, industry and government services, and especially around the region around Rennes.

The topics that will be discussed during the seminar address the study, the analysis, the performance and security evaluation, the validation, and regulatory aspects of all components of secure embedded electronic systems. All these points will be addressed both at theoretical and experimental levels. Among the discussed topics, one can find: basic elements and components in electronic circuits (FPGA, ASIC, smart-cards, micro-controller), associated softwares, cryptographic primitives, crypto-processors and accelerators, secure storage, secure communication on chip, etc. One can also find secure architecture design, hardware/software co-design, performances analysis, security modules (active and passive countermeasures, secure test systems, secure memories, secure communication on chip, etc.), side channel attacks, fault injection attacks, methods and tools for reverse engineering, CAD tools and formal tools for electronic (for design or test), etc.

  • The scientific board is in charge of the organization and the program of the seminar.
    Its members are:

A seminar session will include two 45-minute talks followed by questions. The complete duration (talk + questions) for each presenter will be 1 hour.
If needed, the scientific committee may propose two short 25-minute talks instead of one 45-minute talk.
People attending to this seminar may have very different backgrounds. Then, it is required that the presenter motivates her/his work and provides explanations in a simple and clear language.

Practical infos

Next sessions

  • Hardware Trojan Horses and Microarchitectural Side-Channel Attacks: Detection and Mitigation via Hardware-based
    Methodologies

    • January 24, 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Alessandro PALUMBO - CentraleSupélec, IRISA, Inria

    Hardware Trojan Horses that are software-exploitable can be inserted into microprocessors, allowing attackers to run unauthorized code or escalate privileges. Additionally, it has been demonstrated that attackers could observe certain microprocessor features - seemingly unrelated to the program's execution - to exfiltrate secrets or private data. So, even devices produced in secure foundries could[…]

    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

    • Hardware trojan

  • I know what your compiler did: Optimization Effects on Power Side-Channel Leakage for RISC-V

    • January 24, 2025 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Ileana Buhan - Radboud University Nijmegen

    With the growing prevalence of software-based cryptographic implementations in high-level languages, understanding the role of architectural and micro-architectural components in side-channel security is critical. The role of compilers in case of software implementations towards contribution to side-channel leaks is not investigated. While timing-based side-channel leakage due to compiler effects[…]

    • SemSecuElec

    • Side-channel

  • Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection

    • February 28, 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Alan Díaz Rizo - Sorbonne Université Lip6

    The threat of Hardware Trojan-based Covert Channels (HT-CCs) presents a significant challenge to the security of wireless communications. In this work, we generate in hardware and make open-source a dataset for various HT-CC scenarios. The dataset represents transmissions from a HT-infected RF transceiver hiding a CC that leaks information. It encompasses a wide range of signal impairments, noise[…]

    • SemSecuElec

    • Machine learning

    • Hardware trojan

  • Measurement the thermal component of clock jitter used as entropy source by TRNGs

    • February 28, 2025 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Arturo GARAY - STMicroelectronics

    Introduction Measuring the thermal component of clock jitter as an entropy source for True Random Number Generators (TRNGs) is compulsory for the security and evaluation of clock-jitter based TRNGs. However, identifying and isolating the local thermal noise component from other noise sources, particularly flicker noise, while performing a precise measurement remains a challenge. Current[…]

    • SemSecuElec

    • TRNG

  • Cryptanalytical extraction of complex Neural Networks in black-box settings

    • March 28, 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Benoit COQUERET - INRIA, Thales CESTI

    With the widespread development of artifical intelligence, Deep Neural Networks (DNN) have become valuable intellectual property (IP). In the past few years, software and hardware-based attacks targetting at the weights of the DNN have been introduced allowing potential attacker to gain access to a near-perfect copy of the victim's model. However, these attacks either fail against more complex[…]

    • SemSecuElec

    • Side-channel

    • Machine learning

Show previous sessions

Subscribe to the mailing list

A mailing list is available for announcements concerning SemSecuElec seminar's talks.

Subscribe to the mailing list

Page top