Table of contents

Description

Embedded electronic systems and their associated softwares are used in an always increasing number of daily life, industrial and government applications. The security of these systems is a major societal, economic and sovereignty issue. This leads to increasingly activities in research and development by scientists, industry and government services, and especially around the region around Rennes.

The topics that will be discussed during the seminar address the study, the analysis, the performance and security evaluation, the validation, and regulatory aspects of all components of secure embedded electronic systems. All these points will be addressed both at theoretical and experimental levels. Among the discussed topics, one can find: basic elements and components in electronic circuits (FPGA, ASIC, smart-cards, micro-controller), associated softwares, cryptographic primitives, crypto-processors and accelerators, secure storage, secure communication on chip, etc. One can also find secure architecture design, hardware/software co-design, performances analysis, security modules (active and passive countermeasures, secure test systems, secure memories, secure communication on chip, etc.), side channel attacks, fault injection attacks, methods and tools for reverse engineering, CAD tools and formal tools for electronic (for design or test), etc.

  • The scientific board is in charge of the organization and the program of the seminar.
    Its members are:

A seminar session will include two 45-minute talks followed by questions. The complete duration (talk + questions) for each presenter will be 1 hour.
If needed, the scientific committee may propose two short 25-minute talks instead of one 45-minute talk.
People attending to this seminar may have very different backgrounds. Then, it is required that the presenter motivates her/his work and provides explanations in a simple and clear language.

Practical infos

Next sessions

  • HDL simulation for Masked Software Verification

    • May 29, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Quentin Meunier - Sorbonne Univ. Lip6

    Masking is a countermeasure against Side-Channel Attacks (SCA) that aims to ensure that intermediate computations in an algorithm have secret-independent distributions through the use of random variables. This theoretically prevents SCAs, as power consumption is directly linked to the values manipulated by the program or hardware device. Designing a masking scheme is often non-trivial, and a[…]

    • SemSecuElec

    • Side-channel

  • Étude, caractérisation et détection de verrouillage d'anneaux oscillants utilisés dans les générateurs de nombres aléatoires.

    • May 29, 2026 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Eloise Delolme - LabHC

    Les générateurs de nombres aléatoires matériels basés sur des oscillateurs en anneau (RO-TRNGs) exploitent le jitter d’horloge comme source d’aléa afin de produire des séquences de bits aléatoires. Parmi ces architectures, le MURO-TRNG repose sur un modèle stochastique complexe qui suppose notamment l’indépendance des oscillateurs. Toutefois, dans la pratique, les oscillateurs en anneau sont[…]

    • SemSecuElec

    • TRNG

  • Chamois: Formally verified compilation for optimisation and security

    • June 26, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : David MONNIAUX - CNRS - Verimag

    Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]

    • SemSecuElec

    • Fault injection

    • Formal methods

  • Securing processor's microarchitecture against SCA in a post-quantum cryptography setting

    • October 16, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Vincent MIGLIORE - LAAS-CNRS

    Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]

    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

Previous session

Post-Quantum Cryptography Accelerated by a Superscalar RISC-V Processor

  • April 24, 2026 (11:00 - 12:00)

  • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

Speaker : Côme Allart - Inria

Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.In this context, this thesis investigates the improvement of embedded processor performance, generally for[…]

  • SemSecuElec

  • Implementation of cryptographic algorithm

Show previous sessions

Subscribe to the mailing list

A mailing list is available for announcements concerning SemSecuElec seminar's talks.

Subscribe to the mailing list

Page top