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4 résultats

    • Séminaire

    • Cryptographie

    Cryptanalysis of full BEANIE

    • 05 juin 2026 (13:45 - 14:45)

    • IRMAR - Université de Rennes - Campus Beaulieu Bat. 22, RDC, Rennes - Amphi Lebesgue

    Orateur : Xavier Bonnetain - Inria

    BEANIE is a tweakable block cipher recently published at ToSC aiming for memory encryption of microcontroller units. In line with this goal, it handles small plaintexts of only 32 bits and has a low latency. In this paper, we propose the first third-party analysis of the two variants of BEANIE. By carefully leveraging structural properties of the cipher and taking advantage of its distinctive[…]
    • Cryptography

    • Symmetrical primitive

    • Séminaire

    • SemSecuElec

    Chamois: Formally verified compilation for optimisation and security

    • 26 juin 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : David MONNIAUX - CNRS - Verimag

    Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]
    • SemSecuElec

    • Fault injection

    • Formal methods

    • Séminaire

    • SemSecuElec

    Security of Smart Dust: Robust Key Derivation for Single-Chip Systems

    • 26 juin 2026 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : Sara Faour - Inria

    The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM[…]
    • Séminaire

    • SemSecuElec

    Securing processor's microarchitecture against SCA in a post-quantum cryptography setting

    • 16 octobre 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : Vincent MIGLIORE - LAAS-CNRS

    Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]
    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities