Sommaire

  • Cet exposé a été présenté le 18 octobre 2024 (10:00 - 11:00).

Description

  • Orateur

    Théophile Gousselot - Mines Saint-Etienne, CEA, Leti, Centre CMP, F - 13541 Gardanne France

Embedded devices face software and physical fault injections to either extract or tamper with code in memory. The code execution and code intellectual property are threatened. Some existing countermeasures provide Control Flow Integrity (CFI) extended with the confidentiality and integrity of the instructions by chaining all of them through a cryptographic encryption primitive. While tampering with instructions in memory is prevented, fault injection attacks can still target the microarchitecture. In this talk, we introduce a new chained instruction encryption scheme with associated control signals, to provide additional authenticity and integrity properties down to the control signals of the microarchitecture’s pipeline. The instructions are stored encrypted in memory. At runtime, prior to being executed, the fetched instructions are decrypted depending on the control signals in the pipeline and all the previously decrypted instructions. In case of fault injections, targeting either instructions or control signals, the decryption process fails and generates random instructions, instead of the original ones. This quickly leads to an invalid instruction exception: the fault attack is thwarted. Our scheme was implemented on FPGA, into the 4-stage pipeline of the RISC-V cv32e40p core, using Ascon for encryption/decryption.

Infos pratiques

Prochains exposés

  • FeFET based Logic-in-Memory design, methodologies, tools and open challenges

    • 29 novembre 2024 (10:00 - 11:00)

    • Inria Center of the University of Rennes - - Aurigny room

    Orateur : Cédric Marchand - University of Lyon - Lyon Institute of Nanotechnology (UMR CNRS 5270)

    Data-centric applications such as artificial intelligence and the Internet of Things (IoT) impose increasingly stringent demands on the performance, the security and the energy efficiency of modern computing architectures. Traditional approaches are often unable to keep pace with these requirements making necessary to explore innovative paradigms such as in-memory computing. This paradigm is[…]

    • SemSecuElec

  • TrustSoC : a heterogeneous secure-by-design SoC architecture

    • 29 novembre 2024 (11:00 - 12:00)

    • Inria Center of the University of Rennes - - Aurigny room

    Orateur : Raphaële Milan - Université Jean Monnet Saint-Etienne, CNRS, Laboratoire Hubert Curien UMR 5516

    Since the 1970s, the complexity of systems on a chip has grown significantly. In order to improve system performance, manufacturers are integrating an increasing number of heterogeneous components on a single silicon chip. The incorporation of these components renders SoCs highly versatile yet significantly complex. Their multipurpose nature makes them suitable for use in a variety of domains,[…]

    • SemSecuElec

  • The influence of flicker noise on ring oscillator-based TRNGs

    • 20 décembre 2024 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Licinius-Pompiliu BENEA - Univ. Grenoble Alpes, CEA, LETI

    Ring oscillators (ROs) are often used in true random number generators (TRNGs). The jitter of their clock signal, used as a source of randomness, stems from thermal and flicker noises. While thermal noise jitter is often identified as the main source of randomness, flicker noise jitter is not taken into account due to its autocorrelated nature which greatly complexifies modelling. However, it is a[…]

    • SemSecuElec

    • GDAv

  • Hardware Trojan Horses and Microarchitectural Side-Channel Attacks: Detection and Mitigation via Hardware-based
    Methodologies

    • 24 janvier 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Alessandro PALUMBO - CentraleSupélec, IRISA, Inria

    Hardware Trojan Horses that are software-exploitable can be inserted into microprocessors, allowing attackers to run unauthorized code or escalate privileges. Additionally, it has been demonstrated that attackers could observe certain microprocessor features - seemingly unrelated to the program's execution - to exfiltrate secrets or private data. So, even devices produced in secure foundries could[…]

    • SemSecuElec

    • Canaux auxiliaires

    • Vulnérabilités micro-architecturales

    • Cheval de Troie matériel

  • Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection

    • 28 février 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Alan Díaz Rizo - Sorbonne Université Lip6

    The threat of Hardware Trojan-based Covert Channels (HT-CCs) presents a significant challenge to the security of wireless communications. In this work, we generate in hardware and make open-source a dataset for various HT-CC scenarios. The dataset represents transmissions from a HT-infected RF transceiver hiding a CC that leaks information. It encompasses a wide range of signal impairments, noise[…]

    • SemSecuElec

    • Apprentissage machine

    • Cheval de Troie matériel

  • Cryptanalytical extraction of complex Neural Networks in black-box settings

    • 28 mars 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Benoit COQUERET - INRIA, Thales CESTI

    With the widespread development of artifical intelligence, Deep Neural Networks (DNN) have become valuable intellectual property (IP). In the past few years, software and hardware-based attacks targetting at the weights of the DNN have been introduced allowing potential attacker to gain access to a near-perfect copy of the victim's model. However, these attacks either fail against more complex[…]

    • SemSecuElec

    • Canaux auxiliaires

    • Apprentissage machine

Voir les exposés passés
Haut de page