Description
Data-centric applications such as artificial intelligence and the Internet of Things (IoT) impose increasingly stringent demands on the performance, the security and the energy efficiency of modern computing architectures. Traditional approaches are often unable to keep pace with these requirements making necessary to explore innovative paradigms such as in-memory computing. This paradigm is particularly promising as it minimizes the data movement between memory and processing units, one of the most important bottleneck in conventional systems. Ferroelectric transistors (FeFETs) are at the forefront of this innovation, pushing the boundaries by enabling the development of intrinsically non-volatile logic gates. These gates enables tight integration of memory and logic. This concept is known as Logic in Memory (LiM) and offers a significant reduction of energy consumption while improving computational speed at the same time.
However, the transition from concept to application is far from easy and a lot of challenges have yet to be overcome. Designing non-volatile logic gates is just the first step; these components must also be integrated into complete, functioning architectures capable of handling complex operations, such as cryptographic algorithms. The methodology we propose addresses these challenges by outlining a process for designing such operations using FeFETs, embedding them within a full-scale computing framework, and rigorously evaluating their performance and benefits. Furthermore, the development of these LiM structures raises new issues in logic synthesis, requiring the adaptation of existing synthesis tools or the creation of new ones. Addressing these challenges is crucial for the successful implementation of LiM-based systems in real-world applications.
Infos pratiques
Prochains exposés
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TrustSoC : a heterogeneous secure-by-design SoC architecture
Orateur : Raphaële Milan - Université Jean Monnet Saint-Etienne, CNRS, Laboratoire Hubert Curien UMR 5516
Since the 1970s, the complexity of systems on a chip has grown significantly. In order to improve system performance, manufacturers are integrating an increasing number of heterogeneous components on a single silicon chip. The incorporation of these components renders SoCs highly versatile yet significantly complex. Their multipurpose nature makes them suitable for use in a variety of domains,[…]-
SemSecuElec
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The influence of flicker noise on ring oscillator-based TRNGs
Orateur : Licinius-Pompiliu BENEA - Univ. Grenoble Alpes, CEA, LETI
Ring oscillators (ROs) are often used in true random number generators (TRNGs). The jitter of their clock signal, used as a source of randomness, stems from thermal and flicker noises. While thermal noise jitter is often identified as the main source of randomness, flicker noise jitter is not taken into account due to its autocorrelated nature which greatly complexifies modelling. However, it is a[…]-
SemSecuElec
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GDAv
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Hardware Trojan Horses and Microarchitectural Side-Channel Attacks: Detection and Mitigation via Hardware-based
MethodologiesOrateur : Alessandro PALUMBO - CentraleSupélec, IRISA, Inria
Hardware Trojan Horses that are software-exploitable can be inserted into microprocessors, allowing attackers to run unauthorized code or escalate privileges. Additionally, it has been demonstrated that attackers could observe certain microprocessor features - seemingly unrelated to the program's execution - to exfiltrate secrets or private data. So, even devices produced in secure foundries could[…]-
SemSecuElec
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Canaux auxiliaires
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Vulnérabilités micro-architecturales
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Cheval de Troie matériel
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Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection
Orateur : Alan Díaz Rizo - Sorbonne Université Lip6
The threat of Hardware Trojan-based Covert Channels (HT-CCs) presents a significant challenge to the security of wireless communications. In this work, we generate in hardware and make open-source a dataset for various HT-CC scenarios. The dataset represents transmissions from a HT-infected RF transceiver hiding a CC that leaks information. It encompasses a wide range of signal impairments, noise[…]-
SemSecuElec
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Apprentissage machine
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Cheval de Troie matériel
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Cryptanalytical extraction of complex Neural Networks in black-box settings
Orateur : Benoit COQUERET - INRIA, Thales CESTI
With the widespread development of artifical intelligence, Deep Neural Networks (DNN) have become valuable intellectual property (IP). In the past few years, software and hardware-based attacks targetting at the weights of the DNN have been introduced allowing potential attacker to gain access to a near-perfect copy of the victim's model. However, these attacks either fail against more complex[…]-
SemSecuElec
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Canaux auxiliaires
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Apprentissage machine
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