6 results

  • Malware Detection with AI Systems: bridging the gap between industry and academia

    • October 09, 2025 (11:00)

    • Inria Center of the University of Rennes - Room Aurigny

    Speaker : Luca Demetrio - University of Genova

    With the abundance of programs developed everyday, it is possible to develop next-generation antivirus programs that leverage this vast accumulated knowledge. In practice, these technologies are developed with a mixture of established techniques like pattern matching, and machine learning algorithms, both tailored to achieve high detection rate and low false alarms. While companies state the[…]
    • SoSysec

    • Intrusion detection

    • Machine learning

  • Black-Box Collision Attacks on Widely Deployed Perceptual Hash Functions and Their Consequences

    • October 03, 2025 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Métivier room

    Speaker : Diane Leblanc-Albarel - KU Leuven

    Perceptual hash functions identify multimedia content by mapping similar inputs to similar outputs. They are widely used for detecting copyright violations and illegal content but lack transparency, as their design details are typically kept secret. Governments are considering extending the application of these functions to Client-Side Scanning (CSS) for end-to-end encrypted services: multimedia[…]
    • Cryptography

    • SoSysec

  • NEAT: A Nile-English Aligned Translation Corpus based on a Robust Methodology for Intent Based Networking and Security

    • September 26, 2025 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Room Métivier

    Speaker : Pierre Alain - IUT de Lannion

    The rise of Intent Based Networking (IBN) has paved the way for more efficient network and security management, reduced errors, and accelerated deployment times by leveraging AI processes capable of translating natural language intents into policies or configurations. Specialized neural networks could offer a promising solution at the core of translation operations. Still, they require dedicated,[…]
    • SoSysec

    • Network

    • Security policies

  • Towards privacy-preserving and fairness-aware federated learning framework

    • September 19, 2025 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Petri/Turing room

    Speaker : Nesrine Kaaniche - Télécom SudParis

    Federated Learning (FL) enables the distributed training of a model across multiple data owners under the orchestration of a central server responsible for aggregating the models generated by the different clients. However, the original approach of FL has significant shortcomings related to privacy and fairness requirements. Specifically, the observation of the model updates may lead to privacy[…]
    • Cryptography

    • SoSysec

    • Privacy

    • Machine learning

  • CHERI standardization and software ecosystem

    • September 12, 2025 (11:00 - 12:00)

    • Inria Centre of the University of Rennes - Room Métivier

    Speaker : Carl Shaw - Codasip

    This talk will describe the current status of the RISC-V International standardization process to add CHERI as an official extension to RISC-V. It will then explore the current state of CHERI-enabled operating systems, toolchains and software tool development, focusing on the CHERI-RISC-V hardware implementations of CHERI. It will then go on to give likely future development roadmaps and how the[…]
    • SoSysec

    • SemSecuElec

    • Compartmentalization

    • Operating system and virtualization

    • Hardware/software co-design

    • Hardware architecture

  • CHERI: Architectural Support for Memory Protection and Software Compartmentalization

    • September 12, 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Room Métivier

    Speaker : Robert Watson - University of Cambridge

    CHERI is a processor architecture protection model enabling fine-grained C/C++ memory protection and scalable software compartmentalization. CHERI hybridizes conventional processor, instruction-set, and software designs with an architectural capability model. Originating in DARPA’s CRASH research program in 2010, the work has progressed from FPGA prototypes to the recently released Arm Morello[…]
    • SoSysec

    • SemSecuElec

    • Compartmentalization

    • Hardware/software co-design

    • Hardware architecture