Description
The CHERI ISA extension enables modern RISC CPU architectures such as RISC-V to enforce memory safety in C/C++ programs. Recent academic works use CHERI for point solutions like constructing enclaves, verifying C programs, or hardening bytecode interpreters, but since the original construction of the CHERI-BSD OS - a FreeBSD port leveraging CHERI capabilities, by Cambridge University - little has been reported on what issues and problems arise when porting an existing operating system to benefit from hardware capabilities. This work distills problematic patterns and their solution from what we believe has been the first successful port of a full Linux system to CHERI hardware. In the interest of reproducibility and possible future CHERI or porting style improvements, we also report on the performance impact of our setup.
Practical infos
Next sessions
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A Universal Composability analysis of Android Protected Confirmation
Speaker : Maïwenn Racouchot - CISPA
As phones are used for more and more sensitive operations (such as bank transfers for example), there is a great necessity to design and deploy protocols that can ensure the security of such transactions, even in cases when the phone has been compromised. In order to accomplish that, Android in collaboration with Google have worked on a protocol called Android Protected Confirmation. The idea[…]-
SoSysec
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Formal methods
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Protocols
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