Description
Caches leak information through timing measurements and so-called side-channel attacks. Several primitives exist with different requirements and trade-offs. Flush+Flush is a stealthy and fast cache attack primitive that uses the timing of the clflush instruction depending on the presence of a line in the cache. However, the CPU interconnect plays a bigger role than thought in these timings, and therefore in the error rate of Flush+Flush.
In this paper, we show that a naive implementation that does not take into account the topology of the interconnect yields very important error rates, especially on modern CPUs as the number of cores increases. We, therefore, reverse-engineer this topology and revisit the calibration phase of Flush+Flush for different attacker models to determine the correct threshold for clflush hits and misses. We evaluate that our method yields noiseless side-channel attacks by attacking the AES T-tables implementation of OpenSSL, and by building a covert channel. We obtain a maximal capacity of 3.15 Mbit/s with our improved method, compared to 1.4 Mbit/s with a naive implementation of Flush+Flush on an Intel Core i9-9900 CPU.
Next sessions
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FeFET based Logic-in-Memory design, methodologies, tools and open challenges
Speaker : Cédric Marchand - University of Lyon - Lyon Institute of Nanotechnology (UMR CNRS 5270)
Data-centric applications such as artificial intelligence and the Internet of Things (IoT) impose increasingly stringent demands on the performance, the security and the energy efficiency of modern computing architectures. Traditional approaches are often unable to keep pace with these requirements making necessary to explore innovative paradigms such as in-memory computing. This paradigm is[…]-
SemSecuElec
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TrustSoC : a heterogeneous secure-by-design SoC architecture
Speaker : Raphaële Milan - Université Jean Monnet Saint-Etienne, CNRS, Laboratoire Hubert Curien UMR 5516
Since the 1970s, the complexity of systems on a chip has grown significantly. In order to improve system performance, manufacturers are integrating an increasing number of heterogeneous components on a single silicon chip. The incorporation of these components renders SoCs highly versatile yet significantly complex. Their multipurpose nature makes them suitable for use in a variety of domains,[…]-
SemSecuElec
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The influence of flicker noise on ring oscillator-based TRNGs
Speaker : Licinius-Pompiliu BENEA - Univ. Grenoble Alpes, CEA, LETI
Ring oscillators (ROs) are often used in true random number generators (TRNGs). The jitter of their clock signal, used as a source of randomness, stems from thermal and flicker noises. While thermal noise jitter is often identified as the main source of randomness, flicker noise jitter is not taken into account due to its autocorrelated nature which greatly complexifies modelling. However, it is a[…]-
SemSecuElec
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TRNG
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Hardware Trojan Horses and Microarchitectural Side-Channel Attacks: Detection and Mitigation via Hardware-based
MethodologiesSpeaker : Alessandro PALUMBO - CentraleSupélec, IRISA, Inria
Hardware Trojan Horses that are software-exploitable can be inserted into microprocessors, allowing attackers to run unauthorized code or escalate privileges. Additionally, it has been demonstrated that attackers could observe certain microprocessor features - seemingly unrelated to the program's execution - to exfiltrate secrets or private data. So, even devices produced in secure foundries could[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Hardware trojan
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Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection
Speaker : Alan Díaz Rizo - Sorbonne Université Lip6
The threat of Hardware Trojan-based Covert Channels (HT-CCs) presents a significant challenge to the security of wireless communications. In this work, we generate in hardware and make open-source a dataset for various HT-CC scenarios. The dataset represents transmissions from a HT-infected RF transceiver hiding a CC that leaks information. It encompasses a wide range of signal impairments, noise[…]-
SemSecuElec
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Machine learning
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Hardware trojan
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Cryptanalytical extraction of complex Neural Networks in black-box settings
Speaker : Benoit COQUERET - INRIA, Thales CESTI
With the widespread development of artifical intelligence, Deep Neural Networks (DNN) have become valuable intellectual property (IP). In the past few years, software and hardware-based attacks targetting at the weights of the DNN have been introduced allowing potential attacker to gain access to a near-perfect copy of the victim's model. However, these attacks either fail against more complex[…]-
SemSecuElec
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Side-channel
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Machine learning
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