Description
Data-centric applications such as artificial intelligence and the Internet of Things (IoT) impose increasingly stringent demands on the performance, the security and the energy efficiency of modern computing architectures. Traditional approaches are often unable to keep pace with these requirements making necessary to explore innovative paradigms such as in-memory computing. This paradigm is particularly promising as it minimizes the data movement between memory and processing units, one of the most important bottleneck in conventional systems. Ferroelectric transistors (FeFETs) are at the forefront of this innovation, pushing the boundaries by enabling the development of intrinsically non-volatile logic gates. These gates enables tight integration of memory and logic. This concept is known as Logic in Memory (LiM) and offers a significant reduction of energy consumption while improving computational speed at the same time.
However, the transition from concept to application is far from easy and a lot of challenges have yet to be overcome. Designing non-volatile logic gates is just the first step; these components must also be integrated into complete, functioning architectures capable of handling complex operations, such as cryptographic algorithms. The methodology we propose addresses these challenges by outlining a process for designing such operations using FeFETs, embedding them within a full-scale computing framework, and rigorously evaluating their performance and benefits. Furthermore, the development of these LiM structures raises new issues in logic synthesis, requiring the adaptation of existing synthesis tools or the creation of new ones. Addressing these challenges is crucial for the successful implementation of LiM-based systems in real-world applications.
Practical infos
Next sessions
-
Chamois: Formally verified compilation for optimisation and security
Speaker : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
-
Fault injection
-
Formal methods
-
-
Security of Smart Dust: Robust Key Derivation for Single-Chip Systems
Speaker : Sara Faour - Inria
The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM[…] -
Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Speaker : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
-
Side-channel
-
Micro-architectural vulnerabilities
-
-
Onysis: A secure European SoC FPGA
Speaker : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
-