Table of contents

  • This session has been presented October 18, 2024 (11:00 - 12:00).

Description

  • Speaker

    Lorenzo Casalino - CentraleSupélec, IRISA, Inria (SUSHI team)

The masking countermeasure constitutes a provably secure approach against side-channel attacks. Nonetheless, in the software context, the micro-architecture underlying a given CPU potentially induces information leakages undermining the masking's proven security.

In this seminar, I will present the research work developed during my Ph.D. at CEA-List in Grenoble. This work addresses, along two axes, the problem of developing practically secure masked software.

The first axis targets the automated generation of masked software resilient to transition-based leakages, putting forward the employment of register allocation and instruction scheduling to mitigate such leakages during the compilation of the masked software.

The second axis focuses on the impact of the micro-architecture on alternative types of masking, studying their potential employment as a micro-architecture-independent approach to protect software implementations against both transition-based leakages and data parallelism; this latter an unexplored topic for masked software implementations.

I will conclude the seminar highlighting key points concerning the development of practically secure masked software and potential future developments of my research work.

Next sessions

  • Sécurité physique du mécanisme d'encapsulation de clé Classic McEliece

    • March 20, 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Brice Colombier - Laboratoire Hubert Curien, Université Jean Monnet, Saint-Étienne

    Le mécanisme d'encapsulation de clé Classic McEliece faisait partie des candidats toujours en lice au dernier tour du processus de standardisation de la cryptographie post-quantique initié par le NIST en 2016. Fondé sur les codes correcteurs d'erreurs, en particulier autour du cryptosystème de Niederreiter, sa sécurité n'a pas été fondamentalement remise en cause. Néanmoins, un aspect important du[…]

    • SemSecuElec

    • Implementation of cryptographic algorithm

  • Double Strike: Breaking Approximation-Based Side-Channel Countermeasures for DNNs

    • March 20, 2026 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Lorenzo CASALINO - CentraleSupélec

    Deep neural networks (DNNs) undergo lengthy and expensive training procedures whose outcome - the DNN weights - represents a significant intellectual property asset to protect. Side-channel analysis (SCA) has recently appeared as an effective approach to recover this confidential asset of DNN implementations. Ding et al. (HOST’25) introduced MACPRUNING, a novel SCA countermeasure based on pruning,[…]

    • SemSecuElec

    • Side-channel

  • Protection des processeurs modernes face à la vulnérabilité Spectre

    • April 24, 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Herinomena ANDRIANATREHINA - Inria

    Dans la quête permanente d'une puissance de calcul plus rapide, les processeurs modernes utilisent des techniques permettant d'exploiter au maximum leurs ressources. Parmi ces techniques, l'exécution spéculative tente de prédire le résultat des instructions dont l'issue n'est pas encore connue, mais dont dépend la suite du programme. Cela permet au processeur d'éviter d'être inactif. Cependant,[…]

    • SemSecuElec

    • Micro-architectural vulnerabilities

  • Post-Quantum Cryptography Accelerated by a Superscalar RISC-V Processor

    • April 24, 2026 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Côme Allart - Inria

    Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.In this context, this thesis investigates the improvement of embedded processor performance, generally for[…]

    • SemSecuElec

    • Implementation of cryptographic algorithm

  • Chamois: Formally verified compilation for optimisation and security

    • June 26, 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : David MONNIAUX - CNRS - Verimag

    Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]

    • SemSecuElec

    • Fault injection

    • Formal methods

Show previous sessions
Page top