Description
The masking countermeasure constitutes a provably secure approach against side-channel attacks. Nonetheless, in the software context, the micro-architecture underlying a given CPU potentially induces information leakages undermining the masking's proven security.
In this seminar, I will present the research work developed during my Ph.D. at CEA-List in Grenoble. This work addresses, along two axes, the problem of developing practically secure masked software.
The first axis targets the automated generation of masked software resilient to transition-based leakages, putting forward the employment of register allocation and instruction scheduling to mitigate such leakages during the compilation of the masked software.
The second axis focuses on the impact of the micro-architecture on alternative types of masking, studying their potential employment as a micro-architecture-independent approach to protect software implementations against both transition-based leakages and data parallelism; this latter an unexplored topic for masked software implementations.
I will conclude the seminar highlighting key points concerning the development of practically secure masked software and potential future developments of my research work.
Next sessions
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ML-Based Hardware Trojan Detection in AI Accelerators via Power Side-Channel Analysis
Speaker : Yehya NASSER - IMT Atlantique
Our work discusses the security risks associated with outsourcing AI accelerator design due to the threat of hardware Trojans (HTs), a problem traditional testing methods fail to address. We introduce a novel solution based on Power Side-Channel Analysis (PSCA), where we collect and preprocess power traces by segmenting them and extracting features from both time and frequency domains. This[…]-
SemSecuElec
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Side-channel
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Machine learning
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Hardware trojan
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