Description
Side-Channel Based Disassembly (SCBD) is a category of Side-Channel Analysis (SCA) that aims at recovering information on the code executed by a processor through the observation of physical side-channels such as power consumption or electromagnetic radiations. While traditional SCA often targets cryptographic keys, SCBD focuses on retrieving assembly code that can hardly be extracted via other means. A typical example is bootloader code, which is the first program executed by a processor at a device startup. Finding vulnerabilities in bootloader code could allow an attacker to compromise the entire device. SCBD has been shown feasible on microcontrollers with simple microachitectural complexity and small Instruction Sets Architecture (ISA). However, as System-on-Chips (SoCs) become ubiquitous in various systems such as smartphones, automotive or avionics, the threat posed by SCBD on these devices needs to be evaluated. In this presentation, we investigate the feasibility of SCBD on SoCs. We first study the impact of the microachitectural complexity of SoC's processors on existing SCBD techniques. This brings us to the observation that the latter struggle to provide accurate predictions on small-scale phenomena, leaving a high amount of uncertainty from an attacker's perspective. However, coarse-grained events, such as accesses to the main memory, can be accurately distinguished. In the second part of this presentation, we deal with the uncertainty inherent to SCBD on SoCs by developing a generic and flexible Soft-Analytical Side-Channel Attack (SASCA) framework. This tool leverages factor graphs and the Belief Propagation (BP) algorithm to efficiently handle probabilistic information. This framework allows us to introduce the concept of Soft-Analytical Side-Channel Based Disassembly (SASCBD), which leverages the aforementioned framework to efficiently aggregate imperfect predictions from SCBD. This new approach efficiently exploits the structure of ISA and supports the addition of rich knowledge, such as behaviors at the scale of full programs.
Practical infos
Next sessions
-
Sécurité physique du mécanisme d'encapsulation de clé Classic McEliece
Speaker : Brice Colombier - Laboratoire Hubert Curien, Université Jean Monnet, Saint-Étienne
Le mécanisme d'encapsulation de clé Classic McEliece faisait partie des candidats toujours en lice au dernier tour du processus de standardisation de la cryptographie post-quantique initié par le NIST en 2016. Fondé sur les codes correcteurs d'erreurs, en particulier autour du cryptosystème de Niederreiter, sa sécurité n'a pas été fondamentalement remise en cause. Néanmoins, un aspect important du[…]-
SemSecuElec
-
Implementation of cryptographic algorithm
-
-
Double Strike: Breaking Approximation-Based Side-Channel Countermeasures for DNNs
Speaker : Lorenzo CASALINO - CentraleSupélec
Deep neural networks (DNNs) undergo lengthy and expensive training procedures whose outcome - the DNN weights - represents a significant intellectual property asset to protect. Side-channel analysis (SCA) has recently appeared as an effective approach to recover this confidential asset of DNN implementations. Ding et al. (HOST’25) introduced MACPRUNING, a novel SCA countermeasure based on pruning,[…]-
SemSecuElec
-
Side-channel
-
-
Protection des processeurs modernes face à la vulnérabilité Spectre
Speaker : Herinomena ANDRIANATREHINA - Inria
Dans la quête permanente d'une puissance de calcul plus rapide, les processeurs modernes utilisent des techniques permettant d'exploiter au maximum leurs ressources. Parmi ces techniques, l'exécution spéculative tente de prédire le résultat des instructions dont l'issue n'est pas encore connue, mais dont dépend la suite du programme. Cela permet au processeur d'éviter d'être inactif. Cependant,[…]-
SemSecuElec
-
Micro-architectural vulnerabilities
-
-
Post-Quantum Cryptography Accelerated by a Superscalar RISC-V Processor
Speaker : Côme Allart - Inria
Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.In this context, this thesis investigates the improvement of embedded processor performance, generally for[…]-
SemSecuElec
-
Implementation of cryptographic algorithm
-
-
Chamois: Formally verified compilation for optimisation and security
Speaker : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
-
Fault injection
-
Formal methods
-