Description
Would your latest program produce correct results if I skipped a statement in it? Two? Corrupted a variable at random? Then it might not be robust against _fault injection attacks_, which target hardware directly and have such effects. To be fair, nothing really resists them; still, efforts in designing protections have come a long way, relying (perhaps surprisingly) in large part on hardening code, which is much easier to deploy than new hardware. Of course, modeling the effects of physical tinkering at the abstraction level of a program requires inherent approximations, and recent work has shown that even countermeasures based on assembler-level models (the most common type) can still be bypassed by abusing micro-architectural effects.
In this non-expert talk, I'll discuss fault attacks from a programming-language point of view. The focus will be on conceptualizing what faults and countermeasures mean for programs. I'll show how building a semantic model of a vicious kind of instruction skip leads us to design a mixed software/hardware countermeasure and formally prove it secure. I'll also touch briefly on the challenges of implementing security transformations in the LLVM compiler, which understands security about as well as C (for non-C-programmers, that's not at all). This talk will treat you to both inference rules and linker relocations.
Practical infos
Next sessions
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FeFET based Logic-in-Memory design, methodologies, tools and open challenges
Speaker : Cédric Marchand - University of Lyon - Lyon Institute of Nanotechnology (UMR CNRS 5270)
Data-centric applications such as artificial intelligence and the Internet of Things (IoT) impose increasingly stringent demands on the performance, the security and the energy efficiency of modern computing architectures. Traditional approaches are often unable to keep pace with these requirements making necessary to explore innovative paradigms such as in-memory computing. This paradigm is[…]-
SemSecuElec
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TrustSoC : a heterogeneous secure-by-design SoC architecture
Speaker : Raphaële Milan - Université Jean Monnet Saint-Etienne, CNRS, Laboratoire Hubert Curien UMR 5516
Since the 1970s, the complexity of systems on a chip has grown significantly. In order to improve system performance, manufacturers are integrating an increasing number of heterogeneous components on a single silicon chip. The incorporation of these components renders SoCs highly versatile yet significantly complex. Their multipurpose nature makes them suitable for use in a variety of domains,[…]-
SemSecuElec
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The influence of flicker noise on ring oscillator-based TRNGs
Speaker : Licinius-Pompiliu BENEA - Univ. Grenoble Alpes, CEA, LETI
Ring oscillators (ROs) are often used in true random number generators (TRNGs). The jitter of their clock signal, used as a source of randomness, stems from thermal and flicker noises. While thermal noise jitter is often identified as the main source of randomness, flicker noise jitter is not taken into account due to its autocorrelated nature which greatly complexifies modelling. However, it is a[…]-
SemSecuElec
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TRNG
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Hardware Trojan Horses and Microarchitectural Side-Channel Attacks: Detection and Mitigation via Hardware-based
MethodologiesSpeaker : Alessandro PALUMBO - CentraleSupélec, IRISA, Inria
Hardware Trojan Horses that are software-exploitable can be inserted into microprocessors, allowing attackers to run unauthorized code or escalate privileges. Additionally, it has been demonstrated that attackers could observe certain microprocessor features - seemingly unrelated to the program's execution - to exfiltrate secrets or private data. So, even devices produced in secure foundries could[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Hardware trojan
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Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection
Speaker : Alan Díaz Rizo - Sorbonne Université Lip6
The threat of Hardware Trojan-based Covert Channels (HT-CCs) presents a significant challenge to the security of wireless communications. In this work, we generate in hardware and make open-source a dataset for various HT-CC scenarios. The dataset represents transmissions from a HT-infected RF transceiver hiding a CC that leaks information. It encompasses a wide range of signal impairments, noise[…]-
SemSecuElec
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Machine learning
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Hardware trojan
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Cryptanalytical extraction of complex Neural Networks in black-box settings
Speaker : Benoit COQUERET - INRIA, Thales CESTI
With the widespread development of artifical intelligence, Deep Neural Networks (DNN) have become valuable intellectual property (IP). In the past few years, software and hardware-based attacks targetting at the weights of the DNN have been introduced allowing potential attacker to gain access to a near-perfect copy of the victim's model. However, these attacks either fail against more complex[…]-
SemSecuElec
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Side-channel
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Machine learning
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