Description
Would your latest program produce correct results if I skipped a statement in it? Two? Corrupted a variable at random? Then it might not be robust against _fault injection attacks_, which target hardware directly and have such effects. To be fair, nothing really resists them; still, efforts in designing protections have come a long way, relying (perhaps surprisingly) in large part on hardening code, which is much easier to deploy than new hardware. Of course, modeling the effects of physical tinkering at the abstraction level of a program requires inherent approximations, and recent work has shown that even countermeasures based on assembler-level models (the most common type) can still be bypassed by abusing micro-architectural effects.
In this non-expert talk, I'll discuss fault attacks from a programming-language point of view. The focus will be on conceptualizing what faults and countermeasures mean for programs. I'll show how building a semantic model of a vicious kind of instruction skip leads us to design a mixed software/hardware countermeasure and formally prove it secure. I'll also touch briefly on the challenges of implementing security transformations in the LLVM compiler, which understands security about as well as C (for non-C-programmers, that's not at all). This talk will treat you to both inference rules and linker relocations.
Practical infos
Next sessions
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Speaker : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Onysis: A secure European SoC FPGA
Speaker : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components
Speaker : Luc NOIZETTE - Nuclétudes (filiale Ariane group)
This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform. A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks. Applying it to test softwares[…]-
SemSecuElec
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Fault injection
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