Description
In this seminar I will first discuss unique computer aided design (CAD) compatible SCA security mechanisms. I will present an approach which can significantly increase the physical security-level of a design, be implemented with conventional design-tools and which does not require any special technological-support. The method consists with a correct by-design utilization of power-management libraries and tools; it embeds special and ultra low-cost randomization mechanisms in a local fashion into the RTL of a design. Therefore, making it mature and easy to master by any backend/frontend digital designer. This method is ideally suited for high security levels when used as a building block to reduce the SNR and amplify the noise in the leakage with mathematical solutions (e.g. masking). Theoretically, a limitation of the construction as a stand-alone is security-energy scaling, i.e. for very high security levels its energy cost is exponential. I will present a glimpse of our current work answering this challenge with an alternative construction which provide linear cost.
In the second part of the talk, I will discuss the threat of externally amplified coupling (EAC) attacks. A type of attack which is very dangerous for masked designs as it merges shares leakage which are otherwise supposed to be independent (weather hardware or software). I will review some of our work on the topic and will discuss the scalability of EAC attacks to high order masking designs, its dominance as compared to inherent (intra device) coupling and I will show some results from current experimentation with a dedicated ASIC test bad. Interestingly, the first and second part of the talk share a link which will be discussed.
Next sessions
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FeFET based Logic-in-Memory design, methodologies, tools and open challenges
Speaker : Cédric Marchand - University of Lyon - Lyon Institute of Nanotechnology (UMR CNRS 5270)
Data-centric applications such as artificial intelligence and the Internet of Things (IoT) impose increasingly stringent demands on the performance, the security and the energy efficiency of modern computing architectures. Traditional approaches are often unable to keep pace with these requirements making necessary to explore innovative paradigms such as in-memory computing. This paradigm is[…]-
SemSecuElec
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TrustSoC : a heterogeneous secure-by-design SoC architecture
Speaker : Raphaële Milan - Université Jean Monnet Saint-Etienne, CNRS, Laboratoire Hubert Curien UMR 5516
Since the 1970s, the complexity of systems on a chip has grown significantly. In order to improve system performance, manufacturers are integrating an increasing number of heterogeneous components on a single silicon chip. The incorporation of these components renders SoCs highly versatile yet significantly complex. Their multipurpose nature makes them suitable for use in a variety of domains,[…]-
SemSecuElec
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The influence of flicker noise on ring oscillator-based TRNGs
Speaker : Licinius-Pompiliu BENEA - Univ. Grenoble Alpes, CEA, LETI
Ring oscillators (ROs) are often used in true random number generators (TRNGs). The jitter of their clock signal, used as a source of randomness, stems from thermal and flicker noises. While thermal noise jitter is often identified as the main source of randomness, flicker noise jitter is not taken into account due to its autocorrelated nature which greatly complexifies modelling. However, it is a[…]-
SemSecuElec
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TRNG
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Hardware Trojan Horses and Microarchitectural Side-Channel Attacks: Detection and Mitigation via Hardware-based
MethodologiesSpeaker : Alessandro PALUMBO - CentraleSupélec, IRISA, Inria
Hardware Trojan Horses that are software-exploitable can be inserted into microprocessors, allowing attackers to run unauthorized code or escalate privileges. Additionally, it has been demonstrated that attackers could observe certain microprocessor features - seemingly unrelated to the program's execution - to exfiltrate secrets or private data. So, even devices produced in secure foundries could[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Hardware trojan
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Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection
Speaker : Alan Díaz Rizo - Sorbonne Université Lip6
The threat of Hardware Trojan-based Covert Channels (HT-CCs) presents a significant challenge to the security of wireless communications. In this work, we generate in hardware and make open-source a dataset for various HT-CC scenarios. The dataset represents transmissions from a HT-infected RF transceiver hiding a CC that leaks information. It encompasses a wide range of signal impairments, noise[…]-
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Machine learning
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Hardware trojan
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Cryptanalytical extraction of complex Neural Networks in black-box settings
Speaker : Benoit COQUERET - INRIA, Thales CESTI
With the widespread development of artifical intelligence, Deep Neural Networks (DNN) have become valuable intellectual property (IP). In the past few years, software and hardware-based attacks targetting at the weights of the DNN have been introduced allowing potential attacker to gain access to a near-perfect copy of the victim's model. However, these attacks either fail against more complex[…]-
SemSecuElec
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Side-channel
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Machine learning
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