Description
In this seminar I will first discuss unique computer aided design (CAD) compatible SCA security mechanisms. I will present an approach which can significantly increase the physical security-level of a design, be implemented with conventional design-tools and which does not require any special technological-support. The method consists with a correct by-design utilization of power-management libraries and tools; it embeds special and ultra low-cost randomization mechanisms in a local fashion into the RTL of a design. Therefore, making it mature and easy to master by any backend/frontend digital designer. This method is ideally suited for high security levels when used as a building block to reduce the SNR and amplify the noise in the leakage with mathematical solutions (e.g. masking). Theoretically, a limitation of the construction as a stand-alone is security-energy scaling, i.e. for very high security levels its energy cost is exponential. I will present a glimpse of our current work answering this challenge with an alternative construction which provide linear cost.
In the second part of the talk, I will discuss the threat of externally amplified coupling (EAC) attacks. A type of attack which is very dangerous for masked designs as it merges shares leakage which are otherwise supposed to be independent (weather hardware or software). I will review some of our work on the topic and will discuss the scalability of EAC attacks to high order masking designs, its dominance as compared to inherent (intra device) coupling and I will show some results from current experimentation with a dedicated ASIC test bad. Interestingly, the first and second part of the talk share a link which will be discussed.
Next sessions
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HDL simulation for Masked Software Verification
Speaker : Quentin Meunier - Sorbonne Univ. Lip6
Masking is a countermeasure against Side-Channel Attacks (SCA) that aims to ensure that intermediate computations in an algorithm have secret-independent distributions through the use of random variables. This theoretically prevents SCAs, as power consumption is directly linked to the values manipulated by the program or hardware device. Designing a masking scheme is often non-trivial, and a[…]-
SemSecuElec
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Side-channel
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Étude, caractérisation et détection de verrouillage d'anneaux oscillants utilisés dans les générateurs de nombres aléatoires.
Speaker : Eloise Delolme - LabHC
Les générateurs de nombres aléatoires matériels basés sur des oscillateurs en anneau (RO-TRNGs) exploitent le jitter d’horloge comme source d’aléa afin de produire des séquences de bits aléatoires. Parmi ces architectures, le MURO-TRNG repose sur un modèle stochastique complexe qui suppose notamment l’indépendance des oscillateurs. Toutefois, dans la pratique, les oscillateurs en anneau sont[…]-
SemSecuElec
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TRNG
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Chamois: Formally verified compilation for optimisation and security
Speaker : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
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Fault injection
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Formal methods
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Speaker : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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