41 résultats
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Unique CAD-compatible SCA-security mechanisms, externally amplified coupling (EAC) attacks and (some) connection
Orateur : Itamar Levi
In this seminar I will first discuss unique computer aided design (CAD) compatible SCA security mechanisms. I will present an approach which can significantly increase the physical security-level of a design, be implemented with conventional design-tools and which does not require any special technological-support. The method consists with a correct by-design utilization of power-management[…] -
Lattice-based NIST candidates: abstractions and ninja tricks
Orateur : Thomas Prest
I will present the remaining lattice-based candidates for standardization by NIST (2 signature schemes, 5 encryption schemes). At a high level, these can all be interpreted as straightforward instantiations of decades-old paradigms. But when we look under the hood, all of them make design choices which impact their security, efficiency and portability in distinct manners; we will discuss these.[…] -
Code-based postquantum cryptography : candidates to standardization
Orateur : Nicolas Sendrier
At the third round of the NIST standardization process, three candidates remain with a security based on error correcting codes, all are key exchange mechanisms. We will explore them according to their security assumptions and properties. Among them, we find an historical scheme (Classic McEliece), as well as schemes using sparse and quasi-cyclic matrices (BIKE and HQC). We will examine pros and[…] -
Post-Quantum Cryptography Hardware: Monolithic Implementations vs. Hardware-Software Co-Design
Orateur : Markku-Juhani Saarinen
At PQShield, we’ve developed dedicated coprocessor(s) for lattice schemes, hash-based signatures, and code-based cryptography. These cryptographic modules are commercial rather than academic and designed to meet customer specifications such as a specific performance profile or Common Criteria and FIPS security certification requirements.Hardware implementations of legacy RSA and Elliptic Curve[…] -
SideLine and the advent of software-induced hardware attacks
Orateur : Joseph Gravellier
In this talk, we will discuss software-induced hardware attacks and their impact for IoT, cloud and mobile security. More specifically, I will introduce SideLine, a new power side-channel attack vector that can be triggered remotely to infer cryptographic secrets. SideLine is based on the intentional misuse of delay-lines components embedded in SoCs that use external memory. I will explain how we[…] -
Calibration Done Right: Noiseless Flush+Flush Attacks
Orateur : Guillaume Didier
Caches leak information through timing measurements and so-called side-channel attacks. Several primitives exist with different requirements and trade-offs. Flush+Flush is a stealthy and fast cache attack primitive that uses the timing of the clflush instruction depending on the presence of a line in the cache. However, the CPU interconnect plays a bigger role than thought in these timings, and[…]